1. Technical Field:
The invention relates to semiconductor memory storage systems and more particularly to logic drivers for a plurality of output ports on an integrated circuit. Still more particularly, the invention relates to providing sufficient power to the output drivers, particularly where the output drivers may be synchronously switched.
2. Description of the Related Art:
Dynamic random access memory (DRAM) integrated circuits and static random access memory (SRAM) integrated circuits are data storage devices which are accessed, both for reading and writing of data, by the application of address signals. On a computer memory card the address signals are generated by a logic application specific integrated circuit (ASIC) and are applied to the DRAM and SRAM integrated circuits (I.C.) along wire connections interconnecting the integrated circuits. On-chip address signals from the logic ASIC are applied to output port driver circuits to boost the signals for the transfer.
As is well known, device densities on integrated circuits have greatly increased during the 1980's and early 1990's. Integrated circuit designers have exploited this tendency to use each I.C. to perform ever more tasks. Higher speed operation of system buses may require greater performance from a logic ASIC. For example, in the past where one logic ASIC might handle 10 address lines, it may now be designed to handle 20. The complication added by this is delivering sufficient power to the logic ASIC to drive all of the address lines out.
Power delivery problems stem from connecting a large plurality of output driver switching circuits between a single power bus V.sub.DD and a single ground (GND) bus. At contemporary switching frequencies, distances between logic ASIC and the SRAM or DRAM I.C.'s are such that the load for each output port is essentially that imposed by the destination SRAM or DRAM. In other words, the load is a lumped load. Where an interconnection is a lumped load, undesirable voltage ground bounce and current ringing must be limited. Ground bounce is caused by transient currents flowing through the ground bus. This current in turn results in difficult to predict transient voltage level variations along the bus. This can cause unintentional switching of transistors in drivers parallel to those being turned on and off. The effects of ground bounce and current ringing are multiplied in address signal generating circuitry because of the potential for synchronous switching of most, or even all, of the drivers. The standard way to control the effects of ground bounce and current ringing are to reduce the rate of rise of the current pulse of an output signal. Current ringing and ground bounce thus limit circuit performance in terms of speed.
Synchronized switching of drivers also raises the potential of unintentioned inductive coupling between I.C. interconnections, particularly where the signal change on a number of adjacent interconnections moves unidirectionally. Inductive coupling can result in generation of an unintentioned signal on an address line.
The solution of the power delivery problem is not readily handled by providing more than one power bus on the I.C. to isolate one driver from another. Such a solution would be an expensive and undesirable complication in I.C. design.